Recently, various kinds of integrated circuits or electronic circuits, etc. with microcomputers embedded therein have been developed. In such integrated circuits or electronic circuits embedding microcomputers therein, it is necessary to dispose an apparatus for inputting and outputting data to transmit data between the microcomputers.
FIG. 1 is a block view showing such a conventional apparatus for inputting and outputting data. FIG. 2 is a view showing waveforms of signals of respective portions of FIG. 1.
As shown by FIGS. 1 and 2, an outputting section 2 is an outputting means for outputting data D1 and D2 of transmitting paths L1 and L2 to respective data buses DB at a predetermined output timing. The output timing of the output section 2 is decided by a counter circuit 3 and gate circuits 9 and 10. Namely, a reset signal RS and a clock signal CL are respectively provided for the counter circuit 3. The counter circuit 3 starts the counting operation based on the reset signal RS and the clock signal CL, operating the output section 2 based on the counting output of the counting circuit 3. At this time, the gate circuits 9 and 10 receive a direction control signal DC at L (low voltage) level, and data D1 and D2 from the output section 2 are outputted to the data buses DB only in a period during which the direction control signal DC is at the L level.
When the direction control signal DC is set at H(high voltage) level, the respective output sides of the gate circuits 9 and 10 are set to a high impedance state, the data D3 and D4 transmitted through the data buses DB are inputted to an input section 11. The input section 11 carries out the distribution of data D3 and D4 based on the counting output from the counter circuit 3 mentioned above. Namely, data D3 are transmitted to a transmitting path L3 through a data register 11a, and data D4 is transmitted to a transmitting path L4 through a data register 11b.
However, in the conventional example shown in FIG. 1, it is necessary to provide the reset signal RS and the clock signal CL for driving the counter circuit 3, and to provide the direction control signal DC for controlling the gate circuits 9 and 10. Therefore, it has been desired that the number of signal lines for control is reduced as small as possible, in particular, in electronic circuits, etc. in which the number of IO(input and output) ports is limited.